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| E2L0028-17-Y1 Semiconductor Semiconductor MSM514212 5,048-Word 8-Bit Line Memory This version: Jan. 1998 MSM514212 Previous version: Dec. 1996 DESCRIPTION The OKI MSM514212 is a high-performance serial-line memory. It is designed for use in NTSC, PAL or SECAM Video line buffer applications such as digital comb filters in TVs/VTRs, IDTV (Improved Definition Television), time based correction, or other applications that use serial data including facsimiles, digital copy machines, etc. High-reliability and low-power consumption are accomplished by using CMOS dynamic memory cells. It has separate 8-bit-wide serial input and serial output ports that use independent data clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between input and output data streams. A wide range of variable delay bits (40 bits to 5,048 bits) are supported offering greater design flexibility. Internal logic keeps all asynchronous accesses from being delayed by arbitrating the data storage, and data retrieval requirements to provide maximum performance at all times. All input and output signals are TTL compatible, and the MSM514212 is packaged in a standard 400 mil 28-pin plastic ZIP. FEATURES * Single power supply: 5 V 10% * Capacity: 5,048 words 8 bits * Access: I/O asynchronous * Access time: 28 ns (min.) * Cycle time : 28 ns (min.) * Delay bits: Variable (40 to 5,048) * Low current consumption: 30 mA (max.) * Operating voltage range: 4.5 V to 5.5 V * Operating temperature range : 0C to 70C * Package : 28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) (Product : MSM514212-xxZS) xx indicates speed rank. PRODUCT FAMILY Family MSM514212-28 MSM514212-34 MSM514212-50 Cycle Time (Min.) 28 ns 34 ns 50 ns Access Time (Min.) 28 ns 34 ns 40 ns Power Dissipation (Max.) 230 mA 200 mA 170 mA 1/15 Semiconductor MSM514212 PIN CONFIGURATION (TOP VIEW) VSS DIN3 DIN1 VCC DOUT1 1 3 5 7 9 2 4 6 8 VSS DIN2 DIN0 DOUT0 10 DOUT2 12 VSS 14 RE 16 VSS 18 DOUT5 20 DOUT7 22 WE 24 DIN7 26 DIN5 28 WCK DOUT3 11 RR 13 RCK 15 DOUT4 17 DOUT6 19 VCC 21 WR 23 DIN6 25 DIN4 27 28-Pin Plastic ZIP Pin Name WCK WR WE DIN0 - 7 RCK RR RE DOUT0 - 7 VCC VSS Function Write Clock Write Address Reset Write Enable Data Input Read Clock Read Address Reset Read Enable Data Output Power Supply (5 V) Ground (0 V) Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 Semiconductor BLOCK DIAGRAM DOUT0 RCK Read Timing Controller Data-out Buffer RR Read Reset Controller 32-Word Data Register DOUT1 Data-out Buffer DOUT2 Data-out Buffer DOUT3 Data-out Buffer DOUT4 Data-out Buffer DOUT5 Data-out Buffer DOUT6 Data-out Buffer DOUT7 Data-out Buffer RE 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register Read/Write Select Controller 5032 Memory Array 5032 Memory Array 5032 Memory Array 5032 Memory Array 5032 Memory Array 5032 Memory Array 5032 Memory Array 5032 Memory Array Read/Write X Decoder Controller 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register 32-Word Data Register WR Write Reset Controller VBB Generator 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word 16-Word Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register Sub-Register WCK Write Timing Controller Data-in Buffer Data-in Buffer Data-in Buffer Data-in Buffer Data-in Buffer Data-in Buffer Data-in Buffer Data-in Buffer WE MSM514212 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 3/15 Semiconductor MSM514212 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Pin Voltage Relative to Vss Power Supply Voltage Circuit Output Current Operating Temperature Storage Temperature Symbol VT V CC IO T opr T stg Condition at Ta = 25C, Vss at Ta = 25C, Vcc Ta = 25C -- -- Rating -1.0 to 7.0 -1.0 to 7.0 20 0 to 70 -55 to 150 Unit V V mA C C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Temperature Around Symbol V CC V IH V IL Ta Condition -- -- -- -- Min. 4.5 2.4 -1.5 0 Typ. 5.0 -- -- -- Max. 5.5 5.5 0.8 70 Unit V V V C DC Characteristics (On the Recommended Operating Conditions) Parameter Power Supply Current Input Leakage Current Output Leakage Current Output High Level Voltage Output Low Level Voltage Symbol I CC II IO V OH V OL Condition -- VI = 0 to Vcc, Other pins are 0 V VO = 0 to 5.5 V, DOUT high impedance IOH = -1 mA IOL = 2 mA Min. -- -10 -10 2.4 -- Typ. -- -- -- -- -- Max. 30 10 10 -- 0.4 Unit mA A A V V Capacitance Parameter Input Capacitance Output Capacitance Symbol CI CO (VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Condition -- -- Min. -- -- Typ. -- -- Max. 5 7 Unit pF pF 4/15 Semiconductor AC Characteristics (On the Recommended Operating Conditions) MSM514212 Parameter Write Clock Cycle Time Write Clock Pulse Width Write Clock Precharge Time Read Clock Cycle Time Read Clock Pulse Width Read Clock Precharge Time Access Time Cycle Access Time Right After Reset Output Hold Time Output Hold Time Right After Reset Output Low Impedance Period Output High Impedance Period Input Data Setup Time Input Data Hold Time WR/RR Setup Time from WCK/RCK WR/RR Hold Time from WCK/RCK WR/RR Nonselective Time 1 from WCK/RCK WR/RR Nonselective Time 2 from WCK/RCK WE Setup Time from WCK WE Hold Time from WCK WE Nonselective Time 1 from WCK WE Nonselective Time 2 from WCK RE Setup Time from RCK RE Hold Time from RCK RE Nonselective Time 1 from RCK RE Nonselective Time 2 from RCK WE High Level Period RE High Level Period WR Low Level Period (Write Reset Period) WR Low Level Period (Read Reset Period) Transition Time Symbol t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t WCK WCW WCP RCK RCW RCP AC ACR OH OHR LZ HZ DS DH RS RH RN1 -28 -34 -50 Min. Max. Min. Max. Min. Max. 28 1980 34 1980 50 1980 -- 20 -- 11 14 -- -- 20 -- 11 14 -- 28 1980 34 1980 50 1980 -- 20 -- 11 14 -- -- 20 -- 11 14 -- 40 -- 34 -- -- 28 40 -- 34 -- -- 28 -- 5 -- 5 5 -- -- 5 -- 5 5 -- 40 5 34 5 5 28 40 5 34 5 5 28 -- 15 -- 11 14 -- -- 5 -- 5 5 -- -- 15 -- 11 14 -- -- 5 -- 5 5 -- 5 11 11 5 5 11 11 5 5 11 0 0 0 0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 5 14 14 5 5 14 14 5 5 14 0 0 0 0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 5 15 15 5 5 15 15 5 5 15 0 0 0 0 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RN2 WES WEH WEN1 WEN2 RES REH REN1 REN2 WEW REW RSTW RSTR T 5/15 Semiconductor Notes: MSM514212 1. The input voltage reference levels stipulated in the timing specification are VIH = 3.0 V and VIL = 0 V. The tT is the transition time between VIH = 3.0 V and VIL = 0 V. 2. Rise and fall time tT of all the cycles is specified as 5 ns. 3. During asynchronous execution of write and read operation, the difference between the write address and read address must be greater than 40. 4. Since the MSM514212 uses a dynamic memory cell, it can read the data of the written address within 10 ms after the write cycle at that address is completed. 5. The load condition for measurement is based on 1 TTL + 30 pF. 6. All the potential to the power supply/grounding terminals needs to be supplied. 6/15 Semiconductor MSM514212 SIGNAL DESCRIPTIONS Data Inputs (DIN0 - DIN7) Data on these inputs is shifted in on the rising edge of WCK while WE is held at a low level. The data setup and hold times tDS and tDH are referenced to the rising edge of WCK. Data Outputs (DOUT0 - DOUT7) Data is shifted out on these outputs during the rising edge of RCK while RE is held at a low level. The data becomes valid after the access time interval tAC which begins at the rising edge of RCK. Write Address Pointer Reset (WR) If WR is brought to a low level, the next rising edge of WCK resets the write address pointer to the first address location. The write address pointer is automatically reset when the last address location (5048) is clocked. The WR setup, and hold times tRS and tRH are referenced to the rising edge of WCK. Each write operation, which begins after WR, must contain at least 18 active write cycles, i.e. WCK cycles while WE is high. Read Address Pointer Reset (RR) If RR is brought to a low level, the next rising edge of RCK resets the read address pointer to the first address location. The read address pointer is automatically reset when the last address location (5048) is clocked. The RR setup, and hold times tRS and tRH are referenced to the rising edge of WCK. Each read operation, which begins after RR, must contain at least 18 active read cycles, i.e. RCK cycles while RE is high. Write Enable (WE) This pin is used as a gating function for the WCK input. If WE is held low, normal write cycles can occur. If WE is brought to a high level before the next rising edge of WCK, all subsequent write cycles will be inhibited, and the write address pointer remains unchanged. The WE setup and hold times tWES and tWEH are referenced to the rising edge of WCK. Read Enable (RE) This pin is used as a gating function for the RCK input. If RE is brought to a high level before the next rising edge of RCK, all subsequent read cycles are inhibited, and the read address pointer remains unchanged. The data outputs will tri-state after the output buffer turn off delay time tHZ, which begins at the rising edge of RCK. After the disabled cycles are completed, and the RE signal is brought back to a low level, the data output buffers are re-enabled by the next rising edge of RCK. The RE setup, and hold times tRES and tREH are referenced to the rising edge of RCK. Write Clock (WCK) The rising edge of the WCK input latches the data into the internal registers, and also increments the write address pointer when WE is held low. Read Clock (RCK) The rising edge of the RCK input shifts out the data from the internal registers and increments the read address pointer when RE is held low. 7/15 Semiconductor MSM514212 OPERATION MODE Write Cycle When WE input is enabled (at the "L" level), the write cycle is executed by synchronizing it with the WCK clock input. Read and write data is processed by the same clock in the write cycle to carry out the video processing. Data is input after a delay of oneline (5048 bits) is input at the rising edge of the clock in the write cycle. In addition, when the length of the delay is controlled by WE, the value of the delay bits is from 40 to 5048. The WR operation must be performed now to write the last data to memory cell. Read Cycle When RE input is enabled (at the "L" level), the read cycle is executed by synchronizing it with the RCK clock input. Data is output at tAC (or tACR). In addition, when the length of the delay is controlled by RE, the value of the delay bits is from 40 to 5048. Write Reset Cycle Read Reset Cycle When the power supply is on, the address values of the read and write address pointers are at random. Thus, each pointer must be initialized by the RR signal and the WR signal beforehand. Data can be input (to address 0) with the first cycle after this reset operation. Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 ms stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 18 dummy write operations (WCK cycles) and read operations (RCK cycles) must be performed, followed by a WR operation and an RR operation, to properly initialize the write and the read address pointer. Dummy write cycles/WR and dummy read cycles/RR may occur simultaneously. If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is necessary to perform an RR operation plus a minimum of 18 RCK cycles plus another RR operation, and a WR operation plus a minimum of 18 WCK cycles plus another WR operation to properly initialize read and write address pointers. 8/15 Semiconductor MSM514212 TIMING WAVEFORM Write Cycle n cycle t WCK t WCP WCK t WCW tT WE t DS t DH t DS t WEW t DH t WEN1 t WES t WEH t WEN2 n+1 cycle n+2 cycle disable cycle n+3 cycle D IN (n) (n + 1) (n + 2) (n + 3) WR = "H" Level Read Cycle n cycle t RCK t RCP RCK t RCW tT RE t AC t LZ D OUT n+1 cycle n+2 cycle disable cycle n+3 cycle t REN1 t RES t REW t OH t HZ t REH t REN2 t AC t LZ (n) (n + 1) (n + 2) HIGH-Z (n + 3) RR = "H" Level , , - VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL 9/15 Semiconductor Write Reset Cycle MSM514212 n cycle reset cycle 0 cycle 1 cycle - VIH WCK - VIL t RS WR t RN1 t DS DIN t DH t RSTR t RN1 t RH - VIH t RN2 t DS t DH - VIH (n - 1) (n) (0) (1) - VIL - VIL WE = "L" Level Read Reset Cycle n cycle reset cycle 0 cycle 1 cycle - VIH RCK - VIL t RS RR t RN1 t AC D OUT (n - 1) t ACR t OHR (n) t OHR (0) t ACR t OH (0) t RSTW t RH - VIH t RN2 t AC t OH - VIH (1) - VIL - VIL RE = "L" Level Note: In the write reset and read reset cycles, the reset cycle (for the duration of tRSTW, tRSTR) is not necessarily required for the reset operation. 10/15 Semiconductor n Bit Delay Line Timing (1) t WCW t WCP t RCW t RCP WCK RCK t RS WR RR D IN D OUT MSM514212 1 2 t t WCK RCK 0 cycle 1 cycle 2 cycle n-1 cycle n cycle (0') n+1 cycle (1') n+2 cycle (2') n+3 cycle (3') - VIH - VIL t RH - VIH - VIL t DS t DH t DS t DH - VIH - VIL (0) (1) (2) (n-2) (n-1) (0') (1') (2') (3') n cycle t ACR t OHR - VOH - VOL (0) (1) (2) (3) RE, WE = "L" Level 11/15 Semiconductor n Bit Delay Line Timing (2) WCK RCK t RS WR RR D IN D OUT " " ! MSM514212 t t WCK RCK 0 cycle 1 cycle 2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle t WCW t WCP t RCW t RCP - VIH - VIL t RH - VIH - VIL t RS t RH - VIH - VIL t DS t DH t DS t DH - VIH - VIL (0) (1) (2) (n-2) (n-1) (n) (n+1) (n+2) (n+3) n cycle t ACR t OHR - VOH - VOL (0) (1) (2) (3) RE, WE = "L" Level 12/15 Semiconductor n Bit Delay Line Timing (3) WCK RCK t RS WR RR RE D IN D OUT " " ! MSM514212 t WCK t RCK 0 cycle 1 cycle 2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle t WCW t WCP t RCW t RCP - VIH - VIL t RH - VIH - VIL t REH t REN2 - VIH - VIL t DS t DH t DS t DH - VIH - VIL (0) (1) (2) (n-2) (n-1) (n) (n+1) (n+2) (n+3) n cycle t ACR t OHR HIGH-Z - VOH - VOL (0) (1) (2) (3) WE = "L" Level 13/15 Semiconductor 1 H Delay Line Timing t WCW t WCP t RCW t RCP WCK RCK t RS WR RR D IN D OUT MSM514212 1H 2H t t WCK RCK 0 cycle 1 cycle 2 cycle 5047 cycle 5048 cycle (0') 5049 cycle (1') 5050 cycle 5051 cycle (2') (3') - VIH - VIL t RH - VIH - VIL t DS t DH t DS t DH - VIH - VIL (0) (1) (2) 5046 5047 (0') (1') (2') (3') 5048 cycle t AC t OH - VOH - VOL (0) (1) (2) (3) RE, WE = "L" Level 14/15 Semiconductor MSM514212 PACKAGE DIMENSIONS (Unit : mm) ZIP28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.85 TYP. 15/15 |
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